? semiconductor components industries, llc, 2001 october, 2001 rev. 8 1 publication order number: sn74ls377/d sn74ls377 octal d flip-flop with enable the sn74ls377 is an 8-bit register built using advanced low power schottky technology. this register consists of eight d-type flip-flops with a buffered common clock and a buffered common clock enable. ? 8-bit high speed parallel registers ? positive edge-triggered d-type flip flops ? fully buffered common clock and enable inputs ? true and complement outputs ? input clamp diodes limit high speed termination effects guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky http://onsemi.com pdip20 n suffix case 738 20 1 20 1 a = assembly location wl = wafer lot yy = year ww = work week sn74ls377n awlyyww marking diagrams ls377 awlyyww soic20 dw suffix case 751d 1 1 device package shipping ordering information sn74ls377n pdip20 1440 units/box sn74ls377dw soicwide 38 units/rail sn74ls377dwr2 soicwide 2500/tape & reel
sn74ls377 http://onsemi.com 2 connection diagram dip (top view) enable (active low) input data inputs clock (active high going edge) input true outputs complemented outputs e d 0 - d 3 cp q 0 - q 3 q 0 - q 3 0.5 u.l. 0.5 u.l. 0.5 u.l. 10 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 5 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names note: the flatpak version has the same pinouts (connection diagram) as the dual inline package. 18 17 16 15 14 13 1234 56 7 20 19 8 v cc e q 7 d 7 d 6 q 6 d 5 q 5 d 4 q 0 d 0 d 1 q 1 q 2 d 2 d 3 910 q 3 gnd 12 11 q 4 cp logic diagram e enable d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 cp clock cp d q 14 26 7 3 8 4 5 9 12 16 13 17 cp d q cp d q cp d q cp d q cp d q cp d q cp d q 18 15 19 1 11
sn74ls377 http://onsemi.com 3 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v output low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i input high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 1.) 20 100 ma v cc = max i cc power supply current 28 ma v cc = max, note 1 note: with all i nputs open and gnd applied to all data and enable inputs, i cc is measured after a momentary gnd, then 4.5 v is applied to clock. 1. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions f max maximum clock frequency 30 40 mhz v 50v t plh t phl propagation delay, clock to output 17 18 27 27 ns v cc = 5.0 v c l = 15 pf ac setup requirements (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions t w any pulse width 20 ns t s data setup time 20 ns t enable setup inactive e state 10 ns v cc = 5.0 v t s enable setu time active e state 25 ns v cc 5 . 0 v t h any hold time 5.0 ns definition of terms setup time (ts) e is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low-to-high in order to be recognized and transferred to the outputs. hold time (t h ) e is defined as the minimum time following the clock transition from low-to-high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low-to-high and still be recognized.
sn74ls377 http://onsemi.com 4 truth table e cp d n q n q n h x no change no change l h h l l l l h l = low voltage level h = high voltage level x = immaterial ac waveform *the shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1/f max t w t s(h) t h(h) t s(l) t h(l) cp t phl t plh d or e q *
sn74ls377 http://onsemi.com 5 package dimensions n suffix plastic package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc
sn74ls377 http://onsemi.com 6 package dimensions dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
sn74ls377 http://onsemi.com 7 notes
sn74ls377 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls377/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
